In a transceiver, such as a serializer/deserializer (SerDes), a dock delivery system can include a phase-locked loop (PLL) that generates multiphase dock signals. The clock signals can have phase shifts of 0, 90, 180, and 270 degrees. The generated multiphase dock signals are distributed by dock distribution buffers to a phase interpolator. The phase interpolator interpolates the dock signals to provide interpolated dock signals to a clock and data recovery (CDR) circuit, The CDR circuit uses the interpolated clock signals as sampling docks for recovering timing information from the data stream. For optimal performance, the phase interpolator should operate over a wide frequency range and achieve good linearity in terms of minimizing both differential nonlinearity (DNL) and integral nonlinearity (INL).